The subject matter disclosed herein relates to a method of forming an integrated circuit and the structure formed thereby. More specifically, aspects of the invention relate to forming borderless contact to a transistor.
Conventionally, forming self-aligned contacts in transistors having full-metal gates (FMG) involves using a dielectric cap and a high-k material layer over the cap, which acts as an etch-stop layer during the self-alignment process. The dielectric cap and high-k material combination is also useful in forming replacement metal gates (RMG). However, the high-k material must be formed after the dielectric cap in the RMG scenario. In this scenario, the high-k material remains in the final integrated circuit device (including the structure). The presence of this high-k layer in the final integrated circuit device increases the capacitance effects within the integrated circuit. This increased capacitance can adversely affect the performance of the device.